{"id":91,"date":"2022-05-17T15:14:03","date_gmt":"2022-05-17T14:14:03","guid":{"rendered":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/?page_id=91"},"modified":"2022-05-17T15:17:28","modified_gmt":"2022-05-17T14:17:28","slug":"computer-architecture","status":"publish","type":"page","link":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/computer-architecture\/","title":{"rendered":"Computer Architecture"},"content":{"rendered":"

\"\"<\/p>\n

 <\/p>\n

The Processor<\/h2>\n

The processor is responsible for carrying out the\u00a0<\/span>fetch\/execute cycle<\/strong>.<\/span>\u00a0This involves accessing memory locations to read and write data, either before or after execution by the processor.<\/span><\/p>\n

Modern processors are commonly quad core processors. This means that there are actually four processors that make up the central processing unit. At first there was generally only one core on a processor. This evolved to become dual-core (two processors) and now quad-core.<\/span><\/p>\n

\"\"<\/p>\n

The more processors present, the greater the number of tasks that can be processed simultaneously. This is known as parallel processing, as two different processors can process different tasks (threads) at the same time.<\/span><\/span>\u00a0<\/span><\/p>\n

Arithmetic and Logic Unit (ALU)<\/span><\/span>\u00a0<\/span><\/h2>\n

The Arithmetic and Logic Unit is used by the processor to carry out operations that require the use of:<\/span><\/p>\n

    \n
  • Logical operations such as AND, OR, NOT<\/span><\/li>\n
  • Arithmetic operations such as +, -, *, \/<\/span><\/li>\n<\/ul>\n

    Registers<\/h2>\n

    These are very fast temporary storage locations inside the processor which hold:<\/span><\/p>\n

      \n
    • data being processed<\/span><\/li>\n
    • instructions being executed<\/span><\/li>\n
    • addresses of memory locations to be accessed<\/span><\/li>\n<\/ul>\n

      Instruction Register (IR)<\/span><\/b><\/p>\n

      Holds the instruction currently being\u00a0 decoded and executed by\u00a0<\/span>\u00a0the processor<\/span><\/p>\n

      The Accumulator (A)<\/span><\/b><\/p>\n

      Is a data register which holds the accumulated results of calculations performed in the ALU<\/span><\/p>\n

      The program Counter (PC)<\/span><\/b><\/p>\n

      Is a register which holds the address of the main memory location storing the next instruction to be executed<\/span>\u00a0<\/span><\/p>\n

      Buses<\/h2>\n

      A bus is a collection of wires through which data is transmitted from one part of a computer to another.<\/span><\/span>\u00a0<\/span><\/p>\n

      \"\"<\/p>\n

      Address Bus<\/span><\/b><\/h3>\n

      The address bus is uni-directional, meaning that it is concerned with passing an address one way, from the CPU to RAM. The\u00a0<\/span>sole purpose of an address bus is to identify the address<\/strong>\u00a0of the location in cache or main memory that is to be read from or written to. Each location in memory will have its own\u00a0<\/span>unique address<\/strong>, this is known as addressability.<\/span><\/p>\n

      Data Bus<\/span><\/b><\/h3>\n

      The data bus is bi-directional because it can<\/span>\u00a0carry data to main memory from the processor<\/strong><\/span>\u00a0and vice versa<\/strong>. The data bus will transfer data to\/from the address that is held on the address bus.<\/span><\/p>\n

      The amount of data that can be carried by the data bus depends on the word size. Word size describes the width of the data bus. At the moment new processors will usually have a word size of 64 lines, allowing for 2<\/span>64<\/span>\u202fbits to be transferred during each cycle.<\/span><\/p>\n

      Control bus<\/span><\/b><\/h3>\n

      The control bus is used to identify and initiate the instruction to be carried out.\u00a0\u00a0\u00a0<\/span><\/p>\n

      It is not really a bus at all as each line on the bus is used discretely.\u00a0\u00a0 Some of the common lines in the control bus are:<\/span><\/p>\n

        \n
      • Read<\/span><\/li>\n
      • Write<\/span><\/li>\n
      • Clock<\/span><\/li>\n
      • Interrupt<\/span><\/li>\n
      • Reset<\/span><\/li>\n<\/ul>\n

        Fetch and Execute Cycle<\/span><\/b><\/h3>\n

        A program may contain thousands of instructions but the processor can only execute one instruction at a time.\u00a0 The first instruction is fetched from memory in to the processor where it is decoded and executed.\u00a0 Then the second instruction is fetched and then executed and so on until the program ends.\u00a0\u00a0<\/span><\/p>\n

        This is known as the\u00a0<\/span>FETCH \u2013 EXECUTE CYCLE<\/span><\/b>.<\/span><\/p>\n

        \"\"<\/p>\n

         <\/p>\n

        \"\"<\/p>\n","protected":false},"excerpt":{"rendered":"

          The Processor The processor is responsible for carrying out the\u00a0fetch\/execute cycle.\u00a0This involves accessing memory locations to read and write data, either before or after execution by the processor. Modern processors are commonly quad core processors. This means that there are actually four processors that make up the central processing unit. At first there was […]<\/p>\n","protected":false},"author":79984,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-91","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/wp-json\/wp\/v2\/pages\/91","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/wp-json\/wp\/v2\/users\/79984"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/wp-json\/wp\/v2\/comments?post=91"}],"version-history":[{"count":3,"href":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/wp-json\/wp\/v2\/pages\/91\/revisions"}],"predecessor-version":[{"id":101,"href":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/wp-json\/wp\/v2\/pages\/91\/revisions\/101"}],"wp:attachment":[{"href":"https:\/\/blogs.glowscotland.org.uk\/glowblogs\/phshighercomputingscience\/wp-json\/wp\/v2\/media?parent=91"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}